Search - FPGA DDS

[Other resource] FPGA--DDS-PhaseMeasure

Description: Verilog实现的DDS正弦信号发生器和测频测相模块，DDS模块可产生两路频率和相位差均可预置调整的值正弦波，频率范围为20Hz-5MHz，相位范围为0°-359°，测量的数据通过引脚传输给单片机，单片机进行计算和显示。
Platform: | Size: 1371610 | Author: haoren | Hits:

[VHDL-FPGA-Verilog] 基于FPGA的数字频率计

Description: 基于FPGA的数字频率计
Platform: | Size: 393079 | Author: wjh033 | Hits:

[Other] VHDL编程的DDS设计

Description: 运用FPGA 利用数字频率合成的原理设计信号发生器
Platform: | Size: 139 | Author: lianzhupig | Hits:

Description: DDS文件夹内的程序，完成直接数字频率合成功能,有正弦,三角,方波三种波形,并能扫频. 可通过键盘操作设置频率参数和选择波形种类和控制运行. 由两部分组成,"C"文件夹内,是用于在 51 单片机上运行的 C语言程序, "Verilog"文件夹内,是用Verilog语言编写的 FPGA 程序-ewfreytrgrwf reggwrter rgterthhrgdfs rgdgf egrthg rgreaf rtgerf srfefsf frafgsf frghrsrgwgt
Platform: | Size: 28672 | Author: nbonwenli | Hits:

[VHDL-FPGA-Verilog] dds

Description: 基于FPGA的DDS设计，本程序采用verilog HDL语言编写，使用DDS+Pll倍频-The DDS-based FPGA design, the procedures used verilog HDL language, the use of DDS+ Pll frequency
Platform: | Size: 190464 | Author: 赵一 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 基于Verilog的dds设计，已经经过调试，可直接使用-Dds of Verilog-based design, has been testing can be used directly
Platform: | Size: 2041856 | Author: 郭帅 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: FPGA控制AD9854的源文件，verilog，附有简单文档。-FPGA to control the AD9854 source file, verilog, with a simple document.
Platform: | Size: 820224 | Author: 柴佳 | Hits:

[VHDL-FPGA-Verilog] DDSsinROMsample

Description: fpga DDS ROM数据正弦波形正半周采样程序-fpga DDS ROM sinusoidal waveform is a half weeks of data sampling procedures
Platform: | Size: 747520 | Author: caixiang | Hits:

[VHDL-FPGA-Verilog] dds

Description: 采用 DDS技术 ,利用 FPGA 芯片来实现以 DDS模块为核心的正弦波形产生系统的形成过程-Using DDS technology, the use of FPGA chips to achieve the core module DDS sine wave-shaped formation process of generating system
Platform: | Size: 737280 | Author: weiwenty | Hits:

[VHDL-FPGA-Verilog] DDS-FPGA

Description: 基于FPGA的DDS资料！个人搜集的可直接编译-FPGA-based DDS information!
Platform: | Size: 6350848 | Author: eva | Hits:

[Software Engineering] DDS-FM-FPGA

Description: DDS介绍,FM信号发生器的设计!基于DDS技术的FM信号发生器的设计及其FPGA实现-DDS introduced, FM Signal Generator! FM signal based on DDS technology and FPGA Implementation Generator
Platform: | Size: 356352 | Author: 雨夜里 | Hits:

[SCM] DDS

Description: DDS文件夹内的程序，完成直接数字频率合成功能,有正弦,三角,方波三种波形,并能扫频. 可通过键盘操作设置频率参数和选择波形种类和控制运行. 由两部分组成,"C"文件夹内,是用于在 51 单片机上运行的 C语言程序, "Verilog"文件夹内,是用Verilog语言编写的 FPGA 程序.-DDS program folder, complete direct digital frequency synthesis function, sine, triangle, square wave three, and can sweep. Can be set by keyboard operation frequency parameters and select the waveform type and control operation. Consists of two parts, " C" folder, is used to running on the microcontroller in the 51 C language program, " Verilog" folder, is written in Verilog FPGA program.
Platform: | Size: 433152 | Author: 王金 | Hits:

[VHDL-FPGA-Verilog] FPGA-VHDL-DDS

Description: 基于FPGA的DDS波形发生器--程序，如果需要产生输出不同的位数的波形，可以自行修改程序中的rom表中数据位数-FPGA-based waveform generator DDS- procedure, if the number of bits required to generate output of different waveforms in the program can modify data in the table the median rom
Platform: | Size: 1256448 | Author: 许聪 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 毕业设计，基于FPGA的DDS设计与实现模块-FPGA DDS
Platform: | Size: 2440192 | Author: 钟志强 | Hits:

[VHDL-FPGA-Verilog] FPGA-DDS-algorithm

Description: 采用FPGA的DDS算法Verilog程序的实现-FPGA DDS algorithm Verilog program implementation
Platform: | Size: 1982464 | Author: wang | Hits:

[VHDL-FPGA-Verilog] FPGA-DDS

Description: 基于FPGA的DDS实现QuartusII工程和论文-Based on the FPGA DDS QuartusII project and paper
Platform: | Size: 5076992 | Author: 左向利 | Hits:

[Software Engineering] FPGA-DDS-signal-source-design

Description: FPGA实现dds的编程，很直观详细的资料-FPGA DDS signal source design
Platform: | Size: 91136 | Author: 左向利 | Hits:

[Other] DDS

Description: 用FPGA实现的DDS，用法简单，波形稳定(DDS is implemented using FPGA)
Platform: | Size: 1977344 | Author: 刘奔 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 基于FPGA的DDS正弦信号设计，文件中有源代码(Design of DDS based on FPGA)
Platform: | Size: 51200 | Author: hdu | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 可以实现DDS 的正负线性扫频以及在线参数设置(DDS ad9914/ad9915 code)
Platform: | Size: 5120 | Author: preman | Hits:

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[Other resource] FPGA--DDS-PhaseMeasure

[VHDL-FPGA-Verilog] 基于FPGA的数字频率计

[Other] VHDL编程的DDS设计

[SCM] dds

[VHDL-FPGA-Verilog] dds

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] DDSsinROMsample

[VHDL-FPGA-Verilog] dds

[VHDL-FPGA-Verilog] DDS-FPGA

[Software Engineering] DDS-FM-FPGA

[SCM] DDS

[VHDL-FPGA-Verilog] FPGA-VHDL-DDS

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] FPGA-DDS-algorithm

[VHDL-FPGA-Verilog] FPGA-DDS

[Software Engineering] FPGA-DDS-signal-source-design

[Other] DDS

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] DDS

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